The ongoing miniaturization of electronic devices requires sophisticated processes which allow for better line and space density (L/S) without adding significantly to the cost of the thus obtained devices. Line width and inter line distance of 10 μm (10 μm line and space—L/S) or less are currently difficult to achieve with high yield in high volume manufacturing, while sub-micron dimensions are commonplace when silicon processing methods are adopted.
Generally, fine line circuitry is produced by the so-called Semi-Additive Process (SAP). This process consists of providing a substrate with a layer of copper on its (entire) surface. Then, a dry film resist is placed on those portions of the copper layer which shall later act as conductive lines. The redundant copper is removed by an etching step. Finally, the dry film is removed again. This process works well for devices having a copper line thickness of 10 to 30 μm or greater such as high density interconnects and wherein the individual copper lines have similar line widths. When decreasing the size of copper lines below 10 μm the process becomes too unreliable and produces too much scrap to be used economically. When substrates with copper structures of strongly differing line widths are to be formed, the Semi-Additive process suffers from local current density distribution effects which result in nonconformal plating results. The smaller lines often suffer from overburdens while the broader lines are only partly filled.
U.S. Pat. No. 8,268,400 B2 discloses a method of manufacturing fine line structures suitable for IC substrates. The process described therein comprises the steps of a) depositing conductive particles on the surface of a base material, b) electrifying the base material and thereby using the fine particles as cathode, c) electroless plating onto the charged conductive particles. The conductive particles may be deposited in a formulation further comprising a photosensitive resin which may be subjected to an UV-irradiation also using a photo mask to allow for a structuring to be obtained.
EP 0 243 121 A2 concerns a process for the manufacturing of electrically conductive circuit patterns on transparent substrates comprising the steps of a) forming a structured conductive film made of indium tin oxide or antimony doped tin oxide for example by screen printing, b) forming a first non-transparent coat thereon, c) baking the first coat, d) forming a second coat on the entire surface of the substrate, e) optionally, pre-baking the second coat, f) irradiating with a light source from the back of the substrate and thereby curing the part of the second film which is not on top of the first film, g) removing the uncured film, h) optionally, post-baking the second film. The first coat may be an organic polymer containing a dye or a pigment which then inhibits the curing of the second coat in step f) which is placed on top of the first coat. This process is a very arduous process and does not allow for very fine lines to be formed. Further, the document fails to teach any plating process and relates effectively, to three-colour filters used in liquid crystal displays.
Lasers are used widely in the packaging industries nowadays. One paramount advantage of lasers is the focussed beam which even can be used to structure metals or dielectrics. Hence, an alternative to the above-outlines Semi-Additive process is a laser cutting process of dielectrics or electrolytic copper layers formed on substrates. This, however, is a time-consuming process and, therefore, not suitable for any mass market application.
U.S. Pat. No. 7,569,331 B2 teaches a laser-induced structuring process of a layer consisting of a binder, metal nanoparticles and an adsorption propagation material. The binder can be evaporated with the laser and thus, the remaining metal nanoparticles on the surface result in conductive layers (col. 3, I. 52-57) or lines (col. 4, I. 6-20).
US 2005/0276933 A1 relates to a conductive pattern manufacturing method using sources of electromagnetic energy such as lasers. The process comprises a) providing a substrate made of plastic, polyester or glass, b) depositing a gold nanoparticle containing toluene solution selectively by ink-jet printing or on entire parts of the surface, and c) removing volatiles by laser and melting the gold nanoparticles to form a pattern on the substrate. The gold layers can be further structured by microembossing.
WO 2013/024280 A1 teaches the use of a process for the fine line circuit patterns comprising the steps of a) providing a substrate, b) depositing an ink comprising nanoparticles on said substrate, c) heating the ink with a laser in order to remove any volatiles and thereby forming a structured layer of the nanoparticles, and d) removing any uncured nanoparticles from the surface. Furthermore, the thus formed layers can be used to electrolytically deposit copper thereon. This deposition is not directed and will unfavourably increase the size of the thus formed lines and trenches, e.g. in the lateral direction. This lateral growth of the copper trenches results in an undesired decrease of the gaps between the individual copper lines.
US 2003/0146019 A1 discloses a similar method of depositing metallic nanoparticles on a dielectric substrate and sintering these nanoparticles with a laser to yield a conductive pattern thereon. The document remains silent about any further metal deposition on said pattern.
A further common issue in the manufacturing of fine line circuitry is the problem of over-plating. The electrolytic deposition of metals into trenches and holes formed in dielectrics often results in an overburden of metal formed next to such trenches and holes. This is especially the case for panel plating processes but occurs also for the Semi-Additive Process (see above). This is of particular relevance when attempting to fill trenches and holes having dimensions of below 10 μm (line and space). A special form of over-plating is called mushroom plating in the art. This mushroom plating often occurs when small trenches and holes are filled with metals and the metal deposition results in excess plating which has a mushroom-like appearance in a cross-section.